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W83194BR-648 Data Sheet WIBOND CLOCK GENERATOR FOR SIS P4 SERIES CHIPSET
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Publication Release Date: April 13, 2005 Revision 1.1
W83194BR-648
Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ..........................................................................................................1 FEATURES ..................................................................................................................................1 PIN CONFIGURATION ................................................................................................................2 BLOCK DIAGRAM .......................................................................................................................2 PIN DESCRIPTION......................................................................................................................3 5.1 5.2 5.3 5.4 5.5 5.6 5.7 6. 7. Crystal I/O................................................................................................................................. 3 CPU, ZCLK, SDRAM, PCI Clock Outputs............................................................................... 3 I2C Control Interface ................................................................................................................ 4 Fixed Frequency Outputs ........................................................................................................4 Power Management Pins......................................................................................................... 4 Power Pins................................................................................................................................ 5 Hardware MULTSEL0 Selects Function ................................................................................. 5
FREQUENCY SELECTION BY HARDWARE OR SOFTWARE .................................................6 I2C CONTROL AND STATUS REGISTERS ................................................................................7 7.1 7.2 7.3 7.4 7.5 7.6 7.7 7.8 7.9 7.10 7.11 7.12 7.13 7.14 7.15 7.16 7.17 Register 4: Frequency Select (Default = 00H)........................................................................ 7 Register 5: CPU, SDRAM Clock (1 = Enable, 0 = Stopped) (Default = FFH) ....................... 7 Register 6 PCI Clock (1 = Enable, 0 = Stopped) (Default = FFH) ......................................... 8 Register 7 48 MHz, ZCLK, REF Clock (1 = Enable, 0 = Stopped) (Default = FFH) ............. 8 Register 8: AGP Control (1 = Enable, 0 = Stopped) (Default = CEH) ................................... 8 Register 9: Watchdog Control (Default = 00H) ....................................................................... 9 Register 10: Watchdog Timer (Default = 08H) ....................................................................... 9 Register 11: M/N Program (Default = ABH)............................................................................ 9 Register 12: M/N Program (Default = 2FH) ..........................................................................10 Register 13: Spread Spectrum Programming (Default = 1FH) ............................................10 Register 14: Divisor and Step-less Enable Control (Default = 4CH) ...................................10 Register 15: CPU_ZCLK Skew Control (Default = A7H)......................................................11 Register 16: CPU_AGP_SKEW (Default = 1CH) .................................................................11 Register 17: Skew Control (Default = 24H)...........................................................................11 Register 18: Winbond Chip ID (Read Only) (Default = 77H)................................................12 Register 19: Winbond Chip ID (Read Only) (Default = 11H)................................................12 Ratio Selection Table .............................................................................................................13 Block Write Protocol...............................................................................................................14 Block Read Protocol...............................................................................................................14
8.
ACCESS INTERFACE ...............................................................................................................14 8.1 8.2
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W83194BR-648
8.3 8.4 9. 9.1 9.2 9.3 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 10. 10.1 10.2 11. 12. 13. 14. Byte Write Protocol.................................................................................................................14 Byte Read Protocol ................................................................................................................14 Absolute Maximum Ratings...................................................................................................15 General Operating Characteristics ........................................................................................15 Skew Group Timing Clock .....................................................................................................16 CPU 0.7V Electrical Characteristics ......................................................................................16 CPU 1.0V Electrical Characteristics ......................................................................................16 AGP Electrical Characteristics...............................................................................................17 PCI Electrical Characteristics.................................................................................................17 ZCLK Electrical Characteristics .............................................................................................17 SDRAM Electrical Characteristics .........................................................................................18 24M, 48M Electrical Characteristics ......................................................................................18 REF Electrical Characteristics ...............................................................................................18 CPU_STOP# Timing Diagram...............................................................................................19 PCI_STOP# Timing Diagram ................................................................................................19
SPECIFICATIONS .....................................................................................................................15
POWER MANAGEMENT TIMING .............................................................................................19
ORDERING INFORMATION......................................................................................................20 HOW TO READ THE TOP MARKING .......................................................................................20 PACKAGE DRAWING AND DIMENSIONS ...............................................................................21 REVISION HISTORY .................................................................................................................22
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Publication Release Date: April 13, 2005 Revision 1.1
W83194BR-648
1. GENERAL DESCRIPTION
The W83194BR-648 is a Clock Synthesizer for SIS P4 series chipset. W83194BR-648 provides all clocks required for high-speed Intel Pentium 4, and also provides 32 different frequencies of CPU clocks frequency setting. All clocks are externally selectable with smooth transitions. The W83194BR648 makes SDRAM in synchronous or asynchronous frequency with CPU clocks. The W83194BR-648 provides step-less frequency programming by controlling the VCO freq. and the programmable AGP, PCI clock output divisor ratio. AGP and PCI frequency can be fixed to be four kinds of different frequency outputs. A watchdog timer is quipped and when time out, register9 bit5 will be set to 1 for warning. Spread spectrum built in at 0.5% or 0.25% to reduce EMI. Programmable stopping individual clock outputs and frequency selection through I2C interface. The W83194BR-648 accepts a 14.318 MHz reference crystal as its input and runs on a 3.3V supply. High drive PCI CLOCK outputs typically provide greater than 1V /nS slew rate into 30 pF loads. The fixed frequency outputs as REF, 24 MHz, and 48 MHz provide better than 0.5V /nS slew rate.
2. FEATURES
* Supports Intel Pentium 4 CPU with I2C. * 2 pairs of differential CPU clocks * 2 ZCLK for SIS chipsets * 2 AGP clocks * 1 SDRAM output clock for chipset * 8 PCI synchronous clocks * 1 24/48 MHz, 1 48 MHz * 3 REF clocks * Skew --- CPU to SDRAM < 1 ns, PCI to PCI < 500ps, AGP to AGP < 175ps * Smooth frequency switch with selections from 66 to 200 MHz * I2C 2-Wire serial interface and I2C read back * Flexible spread spectrum to reduce EMI * Programmable registers to enable/stop each output * Packaged in 48-pin SSOP
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Publication Release Date: April 13, 2005 Revision 1.1
W83194BR-648
3. PIN CONFIGURATION
VDDR F S 0 & /R E F 0 F S 1 & /R E F 1 F S 2 & /R E F 2 GND X IN XOUT GND ZCLK0 ZCLK1 VDDZ P C I_ S T O P # * VDDPCI F S 3 & /P C IC L K _ F 0 F S 4 & /P C IC L K _ F 1 P C IC L K 0 P C IC L K 1 GND VDDPCI P C IC L K 2 P C IC L K 3 P C IC L K 4 P C IC L K 5 GND 1 2 3 4 5 6 7 8 9 1 1 1 1 1 1 1 1 1 1 2 2 2 2 2 4 4 4 4 4 4 4 4 4 3 3 3 3 3 3 3 3 3 3 2 2 2 2 2 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 VDDSD SDRAM GND C PU_STO P#* C PU C LKT_1 C PUC LKC _1 VDDC GND C PU C LKT_0 C PUC LKC _0 IR E F GND VDDA SD CLK* SDATA* P D # * /V T T _ P W G D GND AG PCLK0 AG PCLK1 VDDAGP VD D48 48M H z 2 4 _ 4 8 M H z /M U L T IS E L 0 * GND
0 1 2 3 4 5 6 7 8 9 0 1 2 3 4
#: Active low *: Internal pull up resistor 120K to VDD &: Internal Pull-down resistor 120K to GND
4. BLOCK DIAGRAM
Driver 48MHz
PLL2
1/2
Mux
24_48MHz
XIN XOUT
XTAL OSC VCOCLK
3
REF0:2
PLL1 Spread Spectrum
3
Stop
3
CPUCLK_T 0:1 CPUCLK_C 0:1
M/N/Ratio S.S.P ROM
VTT_PWGD FS<0:4> Latch & POR
Divider
2
SDRAM
ZCLK 0:1
2
AGPCLK 0:1
8
Stop
PCICLK_F0:1 PCICLK_0:5
PD#* PCI_STOP#* CPU_STOP#* MULTISEL0*
Control Logic & Config Register
Rref I2C interface
SDATA* SDCLK*
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5. PIN DESCRIPTION
BUFFER TYPE SYMBOL DESCRIPTION
IN INtp120k INtd120k OUT OD I/O I/OD # * &
Input Latched input at power up, internal 120K pull up. Latched input at power up, internal 120K pull down. Output Open Drain Bi-directional Pin Bi-directional Pin, Open Drain. Active Low Internal 120k pull-up Internal 120 k pull-down
5.1 Crystal I/O
PIN PIN NAME TYPE DESCRIPTION
6 7
XIN XOUT
IN OUT
Crystal input with internal loading capacitors (18pF) and feedback resistors. Crystal output at 14.318 MHz nominally with internal loading capacitors (18pF).
5.2 CPU, ZCLK, SDRAM, PCI Clock Outputs
PIN PIN NAME TYPE DESCRIPTION
40, 39, 44, 43
CPUCLKT_0 CPUCLKC_0, CPUCLKT_1 CPUCLKC_1, SDRAM PCICLK_F0
OUT
True CPU clock output and Complementary CPU clock output. These pins will be stopped by CPU_STOP# SDRAM clock output, which have syn. or asyn. Frequencies as CPU clocks. The clock phase is the same as CPUCLKT_0 and CPUCLKT_1. PCI free running clock during normal operation. Latched input for FS3 at initial power up for H/W selecting the output frequency. Internal 120K pull-down PCI free running clock during normal operation. Latched input for FS4 at initial power up for H/W selecting the output frequency. Internal 120K pull-down Low skew (< 500 pS) PCI clock outputs. AGP clock outputs for AGP. Z clock outputs for chipset.
47
OUT OUT INtd120k OUT INtd120k OUT OUT OUT
14
FS3& PCICLK_F1
15
FS4&
16, 17, 20, PCICLK [0:5] 21, 22, 23 31, 30 AGPCLK [0:1] 9, 10 ZCLK [0:1]
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W83194BR-648
5.3 I2C Control Interface
PIN PIN NAME TYPE DESCRIPTION
34 35
SDATA* SDCLK*
I/O IN
Serial data of I C 2-wire control interface, Internal 120K pull-up. Serial clock of I2C 2-wire control interface, Internal 120K pull-up.
2
5.4 Fixed Frequency Outputs
PIN PIN NAME TYPE DESCRIPTION
38
IREF
IN
Deciding the reference current for the CPUCLK pairs. The pin was connected to the precision resistor tied to ground to decide the appropriate current. There are two modes to select different current via power on trapping the Pin 26 (MULTISEL0). The table is show as follows. 3.3V, 14.318 MHz reference clock output. Latched input for FS0 at initial power up for H/W selecting the output frequency. Internal 120 K pull- down. 3.3V, 14.318 MHz reference clock output. Latched input for FS1 at initial power up for H/W selecting the output frequency, Internal 120 K pull- down. 3.3V, 14.318 MHz reference clock output. Latched input for FS2 at initial power up for H/W selecting the output frequency. Internal 120 K pull- down. 24 MHz or 48 MHz clock output selected by Register. MULTISEL0* at initial power up for H/W selecting the current multiplier for CPU outputs. Internal 120 K pull-up. 48 MHz output for USB.
REF0 2 FS0& REF1 3 FS1& REF2 4 FS2& 24_48 MHz 26 27 MULTISEL0* 48 MHz
OUT INtd120k OUT INtd120k OUT INtd120k OUT INtp120k OUT
5.5 Power Management Pins
PIN PIN NAME TYPE DESCRIPTION
PD#* 33 VTT_PWGD
IN
Power Down pin, low active all clocks are stopped, internal 120K pull up. Power good input signal comes from ACPI with high active. This 3.3V input is level sensitive strobe used to determine FS [4:0] and MULTISEL0 input are valid and is ready to sample. This pin is high active. CPU clock stop control pin, This pin is low active. Internal 120K pull-up. PCI clock stop control pin, This pin is low active. Internal 120K pull-up.
IN
45 12
CPU_STOP#* PCI_STOP#*
IN IN
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W83194BR-648
5.6 Power Pins
PIN PIN NAME DESCRIPTION
1 11 36 42 29 13,19 48 28 5, 8, 18, 24, 25, 32, 37, 41, 46
VDDR VDDZ VDDA VDDC VDDAGP VDDPCI VDDSD VDD48 GND
Power supply for REF0: 2 3.3V. Power supply for ZCLK 3.3V. Power supply for core logic. 3.3V Power supply for CPUCLK 3.3V. Power supply for AGP outputs. Power supply for PCI outputs. Power supply for SDRAM 3.3V. Power supply for 48/24 MHz outputs. Circuit Ground.
5.7 Hardware MULTSEL0 Selects Function
MULTSEL0 PIN 26 BOARD TARGET TRACE/TERM Z REFERENCE R, IREF = VDD/(3*RR) OUTPUT CURRENT VOH @ Z
0 0 1 1 0 0 1 1
50 60 50 60 50 60 50 60
Rr = 221 1% IREF = 5.00 mA Rr =221 1% IREF = 5.00 mA Rr = 221 1% IREF = 5.00 mA Rr = 221 1% IREF = 5.00 mA Rr = 475 1% IREF = 2.32 mA Rr = 475 1% IREF = 2.32 mA Rr = 475 1% IREF = 2.32 mA Rr = 475 1% IREF = 2.32 mA
Ioh = 4*IREF Ioh = 4*IREF Ioh = 6*IREF Ioh = 6*IREF Ioh = 4*IREF Ioh = 4*IREF Ioh = 6*IREF Ioh = 6*IREF
1.0V @ 50 1.2V @ 60 1.5V @ 50 1.8V @ 60 0.47V @ 50 0.56V @ 60 0.7V @ 50 0.84V @ 60
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W83194BR-648
6. FREQUENCY SELECTION BY HARDWARE OR SOFTWARE
This frequency table is used at power on latched FS [4:0] value or software programming at SSEL [4:0] (Register 4 bit 4 ~ 7, 2)
FS4 FS3 FS2 FS1 FS0 CPU (MHz) SDRAM (MHz) ZCLK (MHz) AGP (MHz) PCI (MHz)
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
100.2 100.2 100.2 100.2 133.6 133.6 133.6 133.7 166.6 166.8 166.8 166.8 199.7 199.7 199.7 200.0 100.2 100.2 100.2 100.2 133.6 133.6 133.6 133.7 166.6 166.8 166.8 166.8 199.7 199.7 199.7 200.0
100.2 133.6 200.5 167.0 100.2 133.6 200.5 167.2 99.9 133.4 222.4 166.8 99.9 133.2 199.7 150.0 100.2 133.6 200.5 167.0 100.2 133.6 200.5 167.2 99.9 133.4 222.4 166.8 99.9 133.2 199.7 150.0
80.2 80.2 80.2 83.5 80.2 80.2 80.2 83.6 83.3 83.4 83.4 83.4 79.9 79.9 79.9 75.0 133.6 133.6 133.6 125.3 133.6 133.6 133.6 133.7 124.9 133.4 133.4 133.4 133.2 133.2 133.2 120.0
66.8 66.8 66.8 62.6 66.8 66.8 66.8 66.9 62.5 66.7 66.7 66.7 66.6 66.6 66.6 66.7 66.8 66.8 66.8 62.6 66.8 66.8 66.8 66.9 62.5 66.7 66.7 66.7 66.6 66.6 66.6 66.7
33.4 33.4 33.4 31.3 33.4 33.4 33.4 33.4 31.2 33.4 33.4 33.4 33.3 33.3 33.3 33.3 33.4 33.4 33.4 31.3 33.4 33.4 33.4 33.4 31.2 33.4 33.4 33.4 33.3 33.3 33.3 33.3
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7. I2C CONTROL AND STATUS REGISTERS
The Register 0~3 are reserved for external clock buffer (The register No. Is increased by 1 if use byte data read/write protocol)
7.1 Register 4: Frequency Select (Default = 00H)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1
SSEL [3] SSEL [2] SSEL [1] SSEL [0] EN_SSEL SSEL [4] EN_SPSP
0 0 0 0 Enable software program FS [4:0]. 0 0 0 = Select frequency by hardware. 1 = Select frequency by software I2C - Bit 4:7, 2. Frequency selection bit 4 Enable Spread Spectrum in the frequency table. 0 = Normal 1 = Spread Spectrum enabled Enable reload safe frequency when the watchdog is timeout. Frequency selection by software via I2C
0
0
EN_SAFE_FREQ
0
0 = reload the FS [4:0] latched pins when watchdog time out. 1 = reload the safe frequency bit defined at Register 9 bit 4~0.
7.2 Register 5: CPU, SDRAM Clock (1 = Enable, 0 = Stopped) (Default = FFH)
BIT PIN NO PWD DESCRIPTION
7 6 5 4 3 2 1 0
47 44, 43 40, 39 15 14 4 3 2
1 1 1 X X X X X
SDRAM output control CPUCLKT/C1 output control CPUCLKT/C0 output control Invert Power on latched value of FS4 pin, Default 1 (Read only) Invert Power on latched value of FS3 pin. Default 1 (Read only) Invert Power on latched value of FS2 pin. Default 1 (Read only) Invert Power on latched value of FS1 pin. Default 1 (Read only) Invert Power on latched value of FS0 pin. Default 1 (Read only)
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W83194BR-648
7.3 Register 6 PCI Clock (1 = Enable, 0 = Stopped) (Default = FFH)
BIT PIN NO PWD DESCRIPTION
7 6 5 4 3 2 1 0
15 14 23 22 21 20 17 16
1 1 1 1 1 1 1 1
PCICLK_F1 output control PCICLK_F0 output control PCICLK 5 output control PCICLK 4 output control PCICLK 3 output control PCICLK 2 output control PCICLK 1 output control PCICLK 0 output control
7.4 Register 7 48 MHz, ZCLK, REF Clock (1 = Enable, 0 = Stopped) (Default = FFH)
BIT PIN NO PWD DESCRIPTION
7 6 5 4 3 2 1 0
27 26 SEL_24 10 9 4 3 2
1 1 1 1 1 1 1 1
48 MHZ output control 24_48 MHz output control 24/48 MHz frequency control 1: 24 MHz. 0: 48 MHz. ZCLK1 output control ZCLK0 output control REF2 output control REF1 output control REF0 output control
7.5 Register 8: AGP Control (1 = Enable, 0 = Stopped) (Default = CEH)
BIT Pin NO PWD DESCRIPTION
7 6 5 4 3 2 1 0 30 31 MULTISEL0 Reserved
1 1 0 0 1 1 X 0
CPUCLKT/C0 Stop control: 0: CPUCLK0 free run 1: CPUCLK0 can stopped by CPU_STOP# CPUCLKT/C1 Stop control: 0: CPUCLK1 free run 1: CPUCLK1 can stopped by CPU_STOP# PCI_F0 Stop control: 0: PCI_F0 free run 1: PCI_F0 can stopped by PCI_STOP# PCI_F1 Stop control: 0: PCI_F1 free run 1: PCI_F1 can stopped by PCI_STOP# AGP_1 output control AGP_0 output control MULTISEL0 trapping pin data read back, Default 1. Reserved
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W83194BR-648
7.6 Register 9: Watchdog Control (Default = 00H)
BIT NAME PWD DESCRIPTION
7 6
Reserved EN_WD
0 0
Reserved Enable Watchdog Timer if set to 1. Set to 0, disable watchdog timer. Read this bit will return a counting state. If timer continues down count, this bit will return 1. Otherwise, this bit will return 0. Watchdog Timeout Status. If the watchdog is started and timer down counts to zero, this bit will be set to 1. Clear this bit to logic 0, If set to 1, when the watchdog is restart in the next time. This bit is Read Only.
5 4 3 2 1 0
WD_TIMEOUT SAF_FREQ [4] SAF_FREQ [3] SAF_FREQ [2] SAF_FREQ [1] SAF_FREQ [0]
0 0 0 0 0 0
Watchdog safe frequency bits. These bits will be reloaded into FS [4:0], if the watchdog is timeout and enable reload safe frequency bits.
7.7 Register 10: Watchdog Timer (Default = 08H)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
WD_TIME [7] WD_TIME [6] WD_TIME [5] WD_TIME [4] WD_TIME [3] WD_TIME [2] WD_TIME [1] WD_TIME [0]
0 0 0 0 1 0 0 0
Watchdog timeout time. The bit resolution is 250 mS. The default time is 8*250 mS = 2.0 seconds. If the watchdog timer is start, this register will be down count. Read this register will return a down count value.
7.8 Register 11: M/N Program (Default = ABH)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
N_DIV [8] TEST2 TEST1 M_DIV [4] M_DIV [3] M_DIV [2] M_DIV [1] M_DIV [0]
1 0 1 0 1 0 1 1
Programmable N divisor value. Bit 7 ~0 are defined in the Register 12. Test bit 2. WINBOND test bit, do not change them. Test bit 1. WINBOND test bit, do not change them.
Programmable M divisor value.
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W83194BR-648
7.9 Register 12: M/N Program (Default = 2FH)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
N_DIV [7] N_DIV [6] N_DIV [5] N_DIV [4] N_DIV [3] N_DIV [2] N_DIV [1] N_DIV [0]
0
0 1 0 1 1 1 1
Programmable N divisor value bit 7 ~0. The bit 8 is defined in Register 11.
7.10 Register 13: Spread Spectrum Programming (Default = 1FH)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
SP_UP [3] SP_UP [2] SP_UP [1] SP_UP [0] SP_DOWN [3] SP_DOWN [2] SP_DOWN [1] SP_DOWN [0]
0 0 0 1 1 1 1 1
Spread Spectrum Up Counter bit 3. Spread Spectrum Up Counter bit 2. Spread Spectrum Up Counter bit 1. Spread Spectrum Up Counter bit 0 Spread Spectrum Down Counter bit 3 Spread Spectrum Down Counter bit 2 Spread Spectrum Down Counter bit 1 Spread Spectrum Down Counter bit 0
7.11 Register 14: Divisor and Step-less Enable Control (Default = 4CH)
BIT NAME PWD DESCRIPTION
7
EN_MN_PROG
0
0: use frequency table 1: use M/N register to program frequency The equation is VCO freq. = 14.318 MHz * (N+4)/ M. When the watchdog timer is timeout, this will be clear. In this time, the frequency is set to hardware default latched or safe frequency set by EN_SFAE_FREQ (Register 4 bit 0).
6 5 4 3 2 1 0
RATIO_SEL [4] RATIO_SEL [3] RATIO_SEL [2] RATIO_SEL [1] RATIO_SEL [0] TEST0 Reserved
1 0 0 1 1 0 0
CPU, PCI, AGP, SDRAM, and ZCLK ratio selection. The ratio is shown as following table.
Test bit 0. WINBOND test bit, do not change them.
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W83194BR-648
7.12 Register 15: CPU_ZCLK Skew Control (Default = A7H)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
CPU_ZCLK_SKEW [2] Reserved Reserved Reserved Reserved Reserved Reserved Reserved
1 0 1 0 0 1 1 1
CPU to ZCLK SKEW control Reserved
Reserved
7.13 Register 16: CPU_AGP_SKEW (Default = 1CH)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
SEL [1] SEL [0] FIX_AGP_PCI CPU_STOP PCI_STOP CPU_AGP_SKEW [2] CPU_AGP_SKEW [1] CPU_AGP_SKEW [0]
0 0 0 1 1 1 0 0
AGP & PCI FIX frequency (PCI = AGP/2) SEL [1:0] for AGP 00: 72 MHZ 01: 64 MHZ 10: 77NHZ 11: 67MHZ 0:normal mode, 1: fix mode CPU_STOP pin read back CPU_STOP pin read back CPU to AGP skew.
7.14 Register 17: Skew Control (Default = 24H)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
CPU_ZCLK_SKEW [1] CPU_ZCLK_SKEW [0] CPU_SDRAM_SKEW [2] CPU_SDRAM_SKEW [1] CPU_SDRAM_SKEW [0] CPU_PCI_SKEW [2] CPU_PCI_SKEW [1] CPU_PCI_SKEW [0]
0 0 1 0 0 1 0 0
CPU to AGP skew
CPU to SDRAM skew
CPU to PCI skew
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W83194BR-648
7.15 Register 18: Winbond Chip ID (Read Only) (Default = 77H)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
CHPI_ID [7] CHPI_ID [6] CHPI_ID [5] CHPI_ID [4] CHPI_ID [3] CHPI_ID [2] CHPI_ID [1] CHPI_ID [0]
0
1 1 1 0 1 1 1
WINBOND Chip ID. W83194BR-648 is 0x77. WINBOND Chip ID. WINBOND Chip ID. WINBOND Chip ID. WINBOND Chip ID. WINBOND Chip ID. WINBOND Chip ID. WINBOND Chip ID.
7.16 Register 19: Winbond Chip ID (Read Only) (Default = 11H)
BIT NAME PWD DESCRIPTION
7 6 5 4 3 2 1 0
SUB_ID [3] SUB_ID [2] SUB_ID [1] SUB_ID [0] VER_ID [3] VER_ID [2] VER_ID [1] VER_ID [0]
0 0 0 1 0 0 0 1
WINBOND Sub-Chip ID. The sub-chip ID of W83194BR-648 is defined as 0001b. WINBOND Sub-Chip ID. WINBOND Sub-Chip ID. WINBOND Sub-Chip ID. WINBOND Version ID. The Version ID of W83194BR-648 is 0001b. WINBOND Version ID. WINBOND Version ID. WINBOND Version ID.
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W83194BR-648
7.17 Ratio Selection Table
Table of CPU, PCI, AGP, SDRAM, and ZCLK clock selection. Reg14 Bit6 SSEL4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Reg14 Bit5 SSEL3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Reg14 Bit4 SSEL2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Reg14 Bit3 SSEL1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Reg14 Bit2 SSEL0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU Ratio 4 4 4 5 3 3 3 5 3 4 4 4 2 2 2 3 4 4 4 5 3 3 3 5 3 4 4 4 2 2 2 3 SDRAM Ratio 4 3 2 3 4 3 2 4 5 5 3 4 4 3 2 4 4 3 2 3 4 3 2 4 5 5 3 4 4 3 2 4 ZCLK Ratio 5 5 5 6 5 5 5 8 6 8 8 8 5 5 5 8 3 3 3 4 3 3 3 5 4 5 5 5 3 3 3 5 AGP Ratio 6 6 6 8 6 6 6 10 8 10 10 10 6 6 6 9 6 6 6 8 6 6 6 10 8 10 10 10 6 6 6 9 PCI Ratio 12 12 12 16 12 12 12 20 16 20 20 20 12 12 12 18 12 12 12 16 12 12 12 20 16 20 20 20 12 12 12 18
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Publication Release Date: April 13, 2005 Revision 1.1
W83194BR-648
8. ACCESS INTERFACE
The W83194BR-648 provides I2C Serial Bus for microprocessor to read/write internal registers. In the W83194BR-648 is provided Block Read/Block Write and Byte-Data Read/Write protocol. The I2C address is defined at 0xD2.
Block Read and Block Write Protocol
8.1 Block Write Protocol
8.2 Block Read Protocol
## In block mode, the command code must filled 8'h00
8.3 Byte Write Protocol
8.4 Byte Read Protocol
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W83194BR-648
9. SPECIFICATIONS
9.1 Absolute Maximum Ratings
Stresses greater than those listed in this table may cause permanent damage to the device. Precautions should be taken to avoid application of any voltage higher than the maximum rated voltages to this circuit. Subjection to maximum conditions for extended periods may affect reliability. Unused inputs must always be tied to an appropriate logic voltage level (Ground or VDD).
PARAMETER RATING
Absolute 3.3V Core Supply Voltage Absolute 3.3V I/O Supple Voltage Operating 3.3V Core Supply Voltage Operating 3.3V I/O Supple Voltage Storage Temperature Ambient Temperature Operating Temperature Input ESD Protection (Human body model)
-0.5V to +4.6V -0.5 V to +4.6 V 3.135V to 3.465V 3.135V to 3.465V -65C to +150C -55C to +125C 0C to +70C 2000V
9.2 General Operating Characteristics
VDDR = VDDZ = VDDA = VDDC = VDDAGP = VDDPCI = VDDSD = VDD48 = 3.3V 5 %, TA = 0C to +70C, Cl = 10pF
PARAMETER
SYM.
MIN.
MAX.
UNITS
TEST CONDITIONS
Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Dynamic Supply Current Input Pin Capacitance Output Pin Capacitance Input Pin Inductance
VIL VIH VOL VOH Idd Cin Cout Lin 2.4 2.0
0.8 0.4
Vdc Vdc Vdc Vdc All outputs using 3.3V power All outputs using 3.3V power CPU = 100 to 200 MHz PCI = 33.3 MHz with load
350 5 6 7
mA pF pF nH
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W83194BR-648
9.3 Skew Group Timing Clock
VDDR = VDDZ = VDDA = VDDC = VDDAGP = VDDPCI = VDDSD = VDD48 = 3.3V 5 %, TA = 0C to +70C, Cl = 10pF
PARAMETER
MIN.
TYP.
MAX.
UNITS
TEST CONDITIONS
CPU to SDRAM Skew CPU (early) to AGP Skew CPU (early) to ZCLK Skew CPU (early) to PCI Skew CPU to CPU Skew AGP to AGP Skew ZCLK to ZCLK Skew PCI to PCI Skew 48 MHz to 48 MHz Skew REF to REF Skew
-2 1 1 1
0 2 2 2
2 4 4 4 150 175 175 500 1000 500
nS nS nS nS pS pS pS pS pS pS
CPU Crossing point to SDRAM at 1.5V CPU Crossing point to AGP at 1.5V CPU Crossing point to ZCLK at 1.5V CPU Crossing point to PCI at 1.5V Crossing point Measured at 1.5V Measured at 1.5V Measured at 1.5V Measured at 1.5V Measured at 1.5V
9.4 CPU 0.7V Electrical Characteristics
VDDA = VDDC= 3.3V 5 %, TA = 0C to +70C, Test load Rs = 33, Rp = 49.9 Cl = 10pF, Vol = 0.14V, Voh = 0.56V, Vr = 475, IRE = 2.32mA, Ioh = 6*IREF
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Absolute Crossing Point Voltages Cycle to Cycle jitter Duty Cycle
175 175 250 45
700 700 550 125 55
pS pS mV pS %
100 to 200 MHz 100 to 200 MHz 100 to 200 MHz 100 to 200 MHz 100 to 200 MHz
9.5 CPU 1.0V Electrical Characteristics
VDDA = VDDC= 3.3V 5 %, TA = 0C to +70C, Test load Rs = 33, Rp = 49.9 Cl = 10pF, Vol = 0.2V, Voh = 0.8V, Vr = 221, IREF = 5.0 mA, Ioh = 4*IREF
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Absolute Crossing Point Voltages Cycle to Cycle Jitter Duty Cycle
300 300 510 45
600 600 760 200 55
pS pS mV pS %
100 to 200 MHz 100 to 200 MHz 100 to 200 MHz 100 to 200 MHz 100 to 200 MHz
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W83194BR-648
9.6 AGP Electrical Characteristics
VDDAGP= 3.3V 5 %, TA = 0C to +70C, Test load, C = 10pF,
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Cycle to Cycle Jitter Duty Cycle Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max.
500 500 45 -33
1600 1600 250 55 -33
pS pS pS % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout = 1.0V Vout = 3.135V Vout = 1.95V Vout = 0.4V
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9.7 PCI Electrical Characteristics
VDDPCI = 3.3V 5 %, TA = 0C to +70C, Test load, Cl = 10pF
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Cycle to Cycle Jitter Duty Cycle Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max.
500 500 45 -33
2000 2000 500 55 -33
pS pS pS % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout = 1.0V Vout = 3.135V Vout = 1.95V Vout = 0.4V
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9.8 ZCLK Electrical Characteristics
VDDZ = 3.3V 5 %, TA = 0C to +70C, Test load, Cl = 10pF
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Cycle to Cycle Jitter Duty Cycle Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max.
500 500 45 -33
1600 1600 250 55 -33
pS pS pS % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout = 1.0V Vout = 3.135V Vout = 1.95V Vout = 0.4V
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Publication Release Date: April 13, 2005 Revision 1.1
W83194BR-648
9.9 SDRAM Electrical Characteristics
VDDSD= 3.3V 5 %, TA = 0C to +70C, Test load, Cl = 10pF
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Cycle to Cycle Jitter Duty Cycle Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max.
500 500 45 -33
1600 1600 250 55 -33
pS pS pS % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout = 1.0V Vout = 3.135V Vout = 1.95V Vout = 0.4V
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9.10 24M, 48M Electrical Characteristics
VDD48 = 3.3V 5 %, TA = 0C to +70C, Test load, Cl = 10pF
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Long Term Jitter Duty Cycle Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max.
1000 1000 45 -29
4000 4000 500 55 -23
pS pS pS % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout = 1.0V Vout = 3.135V Vout = 1.95V Vout = 0.4V
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9.11 REF Electrical Characteristics
VDD48 = 3.3V 5 %, TA = 0C to +70C, Test load, Cl = 10pF
PARAMETER
MIN.
MAX.
UNITS
TEST CONDITIONS
Rise Time Fall Time Cycle to Cycle Jitter Duty Cycle Pull-Up Current Min. Pull-Up Current Max. Pull-Down Current Min. Pull-Down Current Max.
1000 1000 45 -33
4000 4000 1000 55 -33
ps ps ps % mA mA mA mA
Measure from 0.4V to 2.4V Measure from 2.4V to 0.4V Measure 1.5V point Vout=1.0V Vout=3.135V Vout=1.95V Vout=0.4V
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W83194BR-648
10. POWER MANAGEMENT TIMING
10.1 CPU_STOP# Timing Diagram
CPUCLK (Internal) PCICLK (Internal) PCICLK_F CPU_STOP# 1 2 3 4 1 2 3 4
CPUCLK[0:3]
SDRAM
For synchronous Chipset, CPU_STOP# pin is an asynchronous " active low " input pin used to stop the CPU clocks for low power operation. This pin is asserted synchronously by the external control logic at the rising edge of free running PCI clock (PCICLK_F). All other clocks will continue to run while the CPU clocks are stopped. The CPU clocks will always be stopped in a low state and resume output with full pulse width. In this case, CPU locks on latency" is less than 4 CPU clocks and locks off latency" is less then 4 CPU clocks.
10.2 PCI_STOP# Timing Diagram
CPUCLK (Internal) PCICLK (Internal) PCICLK_F PCI_STOP# 1 2 1 2
PCICLK[0:5]
For synchronous Chipset, PCI_STOP# pin is an asynchronous Active low" input pin used to stop the PCICLK [0:4] for low power operation. This pin is asserted synchronously by the external control logic at the rising edge of free running PCI clock (PCICLK_F). All other clocks will continue to run while the PCI clocks are stopped. The PCI clocks will always be stopped in a low state and resume output with full pulse width. In this case, PCI locks on latency" is less than 2 PCI clocks and locks off latency" is less then 2 PCI clocks. Publication Release Date: April 13, 2005 Revision 1.1
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W83194BR-648
11. ORDERING INFORMATION
PART NUMBER PACKAGE TYPE PRODUCTION FLOW
W83194BR-648
48-pin SSOP
Commercial, 0C to +70C
12. HOW TO READ THE TOP MARKING
Version A
W83194BR-648 28051234 342GCA
Version B
W83194BR-648 28051234 342GCB
1st line: Winbond logo and the type number: W83194BR-648 2nd line: Tracking code 2 8051234 2: wafers manufactured in Winbond FAB 2 8051234: wafer production series lot number 3rd line: Tracking code 342 G C A 342: packages made in '2003, week 42 G: assembly house ID; O means OSE, G means GR C: Internal use code A: IC revision All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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W83194BR-648
13. PACKAGE DRAWING AND DIMENSIONS
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Publication Release Date: April 13, 2005 Revision 1.1
W83194BR-648
14. REVISION HISTORY
VERSION DATE PAGE DESCRIPTION
n.a. 0.5 0.6 0.7 1.0 1.1 02/7/03 2/21/03 12/18/03 05/06/04 04/13/2005 22 17~22 All 7~11, 19
All of the versions before 0.50 are for internal use. Add AC/DC Specifications and Power management Update new form Correction IC version, add register default value and correction some description and default value Update on web Add disclaimer
Important Notice
Winbond products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for surgical implantation, atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, or for other applications intended to support or sustain life. Further more, Winbond products are not intended for applications wherein failure of Winbond products could result or lead to a situation wherein personal injury, death or severe property or environmental damage could occur. Winbond customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Winbond for any damages resulting from such improper use or sales.
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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